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Cypress Semiconductor /psoc63 /BLE /BLESS /PWR_CTRL_SM_ST

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Interpret as PWR_CTRL_SM_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PWR_CTRL_SM_CURR_STATE

Description

Link Layer Power Control FSM Status Register

Fields

PWR_CTRL_SM_CURR_STATE

This register reflects the current state of the LL Power Control FSM 4’h0 - IDLE 4’h1 - SLEEP 4’h2 - DEEP_SLEEP 4’h4 - WAIT_OSC_STABLE 4’h5 - INTR_GEN 4’h6 - ACTIVE 4’h7 - REQ_RF_OFF

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data